The present invention relates to semiconductor device metal layer interconnects and more particularly to reducing the contact resistance of interconnects.
A typical integrated circuit contains a plurality of metal pathways to provide electrical power for powering the various semiconductor devices comprising the integrated circuit, and to allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or xe2x80x9cinterlayerxe2x80x9d dielectrics that insulate the metal layers from each other. Typically, however, each metal layer must form electrical contact to an additional metal layer. Metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the first and second metal layers, and by filling the resulting hole or via with a metal to create an interconnect as described further below.
The use of copper in place of aluminum as the interconnect material for semiconductor devices has grown in popularity due to copper""s lower resistivity. Unlike aluminum, however, copper is highly mobile in silicon dioxide and may, as a result of infiltration of copper atoms into the dielectric, create leakage paths through a device""s various dielectric layers. Copper atoms also can cause electrical defects in silicon. Accordingly, as best understood with reference to FIGS. 1A-1C described below, a semiconductor device employing copper interconnects requires the creation of encapsulating barrier layers to prevent deleterious incorporation of copper atoms into the device""s various material layers.
FIGS. 1A-C show sequential cross-sectional views of the formation of a conventional copper interconnect 10 (FIG. 1C) through an aperture in a dielectric layer disposed between two copper layers, a first copper layer 11a disposed within a dielectric layer D and a second copper layer 11b. With reference to FIG. 1A, to form the copper interconnect 10, a silicon dioxide interlayer dielectric 13 is deposited over the first copper layer 11a. A first via 15 then is etched in the interlayer dielectric 13 to expose the first copper layer 11a. 
Copper is highly reactive with oxygen and easily forms a surface layer of high resistivity copper oxide when exposed to an oxygen rich atmosphere. Because the first layer 11a is copper, a high resistance copper oxide layer 11axe2x80x2 can form on the top surface of the first copper layer 11a if the first copper layer 11a is exposed to oxygen or water vapor (e.g., air). This oxidation can occur when the wafers, just having the vias etched therein, are moved from an etch tool to a metallization tool. The copper oxide layer 11a will complete formation once all exposed and unoxidized copper is converted to copper oxide. Accordingly, to minimize the resistance of the copper interconnect 10, the copper oxide layer 11axe2x80x2 must be removed. Typically the copper oxide layer 11axe2x80x2 is removed by sputtering the copper oxide layer 11axe2x80x2 with ions generated within a plasma (i.e., sputter-etching), such as argon ions generated within an argon plasma. The argon ions are accelerated toward the wafer via a negative electric bias imposed on the wafer or on the wafer support. These ions strike the wafer and the copper oxide layer 11axe2x80x2 at the base of the unfilled via, and eject material from the copper oxide layer 11axe2x80x2 (including copper immediately beneath the copper oxide) due to momentum transfer between the accelerated argon ions and the copper oxide layer 11axe2x80x2. 
The ejected material, which includes copper atoms 11axe2x80x3, coats the interlayer dielectric 13 as shown in FIG. 1A. The copper atoms 11axe2x80x3 contained in the ejected material can enter the interlayer dielectric 13 and drift therethrough under the influence of an applied electric field (e.g., a device voltage), causing deleterious interconnect-to-interconnect leakage currents (i.e., via-to-via leakage currents). Such deleterious via-to-via leakage currents, however, cannot be avoided in conventional copper interconnects if the copper oxide layer 11axe2x80x2 is removed. Accordingly, conventional copper interconnects suffer from either a high resistance copper oxide layer 11axe2x80x2 which is left in place to prevent dielectric degradation induced by copper sputtered directly on the wall of the unfilled via, or copper atom induced degradation in the dielectric which leads to via-to-via leakage currents.
Following removal of the copper oxide layer 11axe2x80x2, a thin barrier layer 17 (e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride) is deposited over the interlayer dielectric 13 and the first copper layer 11a as shown in FIG. 1B. The barrier layer 17 prevents copper atoms from a subsequently deposited copper layer (namely the second copper layer 11b of FIG. 1C) from incorporating into, and thus degrading, the interlayer dielectric 13.
To complete the conventional copper interconnect 10, the second copper layer 11b is deposited over the barrier layer 17 either conformally or in the form of a copper plug 11bxe2x80x2, as shown in FIG. 1C. A copper xe2x80x9cseedxe2x80x9d layer (not shown) typically is deposited prior to deposition of the copper plug 11bxe2x80x2. Thus, a conventional copper interconnect 10 consists of the first copper layer 11a xe2x80x9cin contactxe2x80x9d with the second copper layer 11b through the barrier layer 17.
Because the barrier layer 17 can have a resistivity up to 100 times greater than the resistivity of copper, the barrier layer 17 significantly increases the contact resistance of the interconnect 10 formed between the first copper layer 11a and the second copper layer 11b. Therefore, the significant advantage of copper""s lower resistivity is not fully realized due to the presence of barrier layers. The barrier layer 17, however, is required to prevent further incorporation of copper atoms within the interlayer dielectric 13.
In sum, conventional copper interconnects suffer from high resistances due to the presence of barrier layers, and can suffer from via-to-via leakage currents due to sputtered copper atom incorporation in the interlayer dielectric 13 during interconnect formation. Accordingly, a need exists for an improved copper interconnect that does not suffer from either high resistance or via-to-via leakage currents.
The present invention provides an inventive copper interconnect free from copper atom via-to-via leakage current paths and preferably having a significantly reduced resistance. Specifically, in a first aspect, a barrier layer (e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride) is deposited on the exposed first copper layer and on the interlayer dielectric prior to sputter-etching the copper oxide layer. Thereafter, the barrier layer at the bottom of the interlayer dielectric""s via, and the copper oxide layer thereunder, are sputter-etched. Because the barrier layer is deposited prior to sputter-etching, during sputter-etching copper atoms from the copper oxide layer redistribute on the barrier layer rather than on the interlayer dielectric. The copper atoms are not mobile within the barrier layer, and are prevented from diffusing to and contaminating the interlayer dielectric. Accordingly, no via-to-via leakage current paths are created during copper interconnection formation.
Following sputter-etching, the second copper layer is deposited over the barrier layer and the exposed first copper layer to complete copper interconnect formation. Because the first and second copper layers are in direct contact, the high resistivity of the barrier layer is eliminated. Accordingly, the inventive copper interconnect has low resistance in addition to no via-to-via leakage current paths.
In a second aspect, a capping dielectric barrier layer (e.g., silicon nitride) is deposited over the first copper layer prior to interlayer dielectric formation. Preferably, the capping dielectric barrier layer is deposited before the first copper layer is exposed to oxygen (e.g., air) to prevent copper oxide formation on the first copper layer. Thereafter, the capping dielectric barrier layer and any copper oxide formed on the first copper layer are sputter-etched. Because the capping dielectric barrier layer is sputter-etched first, it is redistributed on the sidewalls of the interlayer dielectric and serves as a diffusion barrier to any copper atoms (from the underlying copper oxide layer) that may redistribute on the sidewalls during sputter-etching. The redistributed capping dielectric barrier layer material thus prevents copper atoms from entering the interlayer dielectric and creating via-to-via current leakage paths therein.
The copper interconnect is completed by depositing a barrier layer over the exposed first copper layer, and by depositing a second copper layer over the barrier layer. The presence of the barrier layer between the first and second copper layers increases the copper interconnect""s resistance. However, unlike the prior art, the copper interconnect does not suffer from via-to-via leakage currents. Further, the capping dielectric barrier layer may be used advantageously as an etch stop layer if so desired.
A third aspect of the invention also employs the capping dielectric barrier layer. However, unlike the second aspect, the barrier layer is deposited on the capping dielectric barrier layer and on the interlayer dielectric prior to sputter-etching. Thereafter, the barrier layer, the capping dielectric barrier layer, and any copper oxide formed on the first copper layer are etched, and the second copper layer is deposited directly on the exposed first copper layer, making direct contact therebetween.
Both the barrier layer and the material from the capping dielectric barrier layer which redistributes on the sidewalls of the interlayer dielectric prevent sputter-etched copper atoms from reaching the interlayer dielectric. Via-to-via leakage currents thereby are eliminated. Because the first and second copper layers are in direct contact (the barrier layer having been removed), the inventive copper interconnect has low resistance. Like the second aspect, the capping dielectric barrier layer of the third aspect may serve as an etch stop layer and preferably is deposited prior to exposing the first copper layer to oxygen.
For the first and third aspects, preferably the deposition of the barrier layer on the sidewalls of the interlayer dielectric is performed xe2x80x9csimultaneouslyxe2x80x9d with either the sputter-etching of the copper oxide layer (first aspect) or the capping dielectric barrier layer and the copper oxide layer (third aspect). Simultaneous deposition/sputter-etching may be performed within a high density plasma (HDP) sputtering chamber by adjusting the chamber""s RF coil power and RF wafer bias to achieve the desired deposition/sputter-etching ratio. Alternatively, deposition of the barrier layer and sputter-etching of the copper oxide layer and the capping dielectric barrier layer may be performed xe2x80x9csequentiallyxe2x80x9d within the same chamber or by depositing the barrier layer within a first processing chamber (e.g., an HDP chamber) and by sputter-etching any copper oxide layer and any capping dielectric barrier layer within a separate processing chamber (e.g., a sputter-etching chamber such as Applied Materials"" Preclean II chamber). In either case, deposition of the second copper layer preferably is performed prior to breaking vacuum so as to maintain a copper-oxide free interface between the first and second copper layers.